The present invention relates to integrated circuits and packaged integrated circuits and, more particularly, to a lead frame for a packaged integrated circuit.
An integrated circuit (IC) die is a small device formed on a semiconductor wafer, such as a silicon wafer. Such a die is typically cut from the wafer and packaged using a lead frame. The lead frame is a metal frame, usually of copper or nickel alloy, that supports the IC and provides the external electrical connections for the packaged chip. A lead frame usually includes a flag or die pad, and lead fingers. Bond pads on the die are electrically connected to the leads of the lead frame via wire bonding. The die and bond wires are encapsulated with a protective material to form a package. The leads either project outwardly from the encapsulation or are at least flush with the encapsulation so they can be used as terminals, allowing the IC to be electrically connected to other devices or a printed circuit board (PCB).
Referring to FIG. 1, an enlarged cross-sectional view of a conventional semiconductor device 10 is shown. The device 10 includes a semiconductor die 12 attached to a die pad 14 and electrically coupled to lead fingers 16. The die 12, die pad 14, and parts of the lead fingers 16 are covered with a mold compound 18, which protects the die 12 and the electrical connections to the lead fingers 16 from being damaged. The lead fingers 16 project from the mold compound 18, which allows for external electrical connection of the die 12.
The number of leads is limited by the size of the package and the pitch of the leads. A package with many leads (high I/O count) is more expensive to produce than a package with fewer leads and a greater pitch. However, while there is a continual demand for smaller packages with more leads, decreasing the spacing between leads requires a more complex and more expensive test socket, increases the likelihood of open and short circuit rejects, and out of alignment leads, all of which increase cost. Thus, it would be advantageous to be able to assemble a semiconductor device with more I/Os in the same or a smaller size package while maintaining or lowering package cost.